In a manufacturing process of an electronic device having a multilayer wiring structure, silicon-based insulating films are laminated on an underlying film of a substrate. Then, multilayer films thus formed by laminating the silicon-based insulating films are etched in a shape of groove or hole. Generally, an etching of the multilayer films is performed on a layer by layer basis starting from a top layer by using an etching gas including a CF (carbon fluoride) based reaction gas. However, to enhance throughput, there has been proposed an etching method, in which the multilayer films are etched in a single step. Further in order to reduce excess carbon, an etching gas in which an O2 gas is added to the CF based reaction gas has been used as well.
However, as shown in FIG. 10 (referring to Japanese patent publication No. 200-235973), a multilayer wiring structure in which a number of Al wirings 100 are out of line in up and down direction can be provided in an electronic device. On an upper part of the Al wiring 100, an underlying film 101, and a laminated film 102 of insulating characteristics are formed thereon in turn, and a resist film R which serves as an etching mask is formed thereon. In this case, a coated insulating film 103, which is formed by a coating method such as SOG (Spin On Glass), is provided in the laminated film 102 as a layer thereof such that influence of sheered Al wirings 100 can be eliminated and a surface of the laminated film 102 can be leveled. The coated insulating film 103 is formed by applying liquid coating material and drying it. The thickness of the coated insulating film varies depending on its location such that the top surface thereof may become flat.
When the laminated film 102 including the coated insulating film 103 whose thickness varies depending on its location is etched by a CF based etching gas to which oxygen gas is added, total etching time of the laminated film 102 is influenced by the thickness of the coated insulating film 103, because an etching rate of the coated insulating film 103 is slower than that of other insulating films 104 and 105. In other words, the etching time of the laminated film 102 at a place where the coated insulating film 103 is very thick differs greatly from that at a place where the coated insulating film 103 is very thin.
Time T needed for the underlying film 101 to be exposed after the etching of the laminated film 102 is started varies greatly depending on the location of each Al wiring 100. Sequentially, while the laminated film 102 is etched, some parts of the underlying film 101 may be exposed to the etching gas for a long time so that the underlying film 101 which is not an etching target is etched to some degree, thereby resulting in it being degraded or deteriorated.